Pipeline: improve performance by using direct mode

This commit is contained in:
Aleix Conchillo Flaqué
2025-08-14 15:15:47 -07:00
parent 609a43a191
commit dc7bf98ce5
3 changed files with 7 additions and 3 deletions

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@@ -38,6 +38,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Fixed an issue where `AsyncAITTSService` had very high latency in responding
by adding `force=true` when sending the flush command.
### Performance
- `Pipeline` performance improvements by using direct mode.
### Other
- Added `14w-function-calling-mistal.py` using `MistralLLMService`.

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@@ -19,9 +19,9 @@ class BasePipeline(FrameProcessor):
metrics collection from their contained processors.
"""
def __init__(self):
def __init__(self, **kwargs):
"""Initialize the base pipeline."""
super().__init__()
super().__init__(**kwargs)
@abstractmethod
def processors_with_metrics(self) -> List[FrameProcessor]:

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@@ -98,7 +98,7 @@ class Pipeline(BasePipeline):
Args:
processors: List of frame processors to connect in sequence.
"""
super().__init__()
super().__init__(enable_direct_mode=True)
# Add a source and a sink queue so we can forward frames upstream and
# downstream outside of the pipeline.