From dc7bf98ce5a59334e2b53e801eceee284974298c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Aleix=20Conchillo=20Flaqu=C3=A9?= Date: Thu, 14 Aug 2025 15:15:47 -0700 Subject: [PATCH] Pipeline: improve performance by using direct mode --- CHANGELOG.md | 4 ++++ src/pipecat/pipeline/base_pipeline.py | 4 ++-- src/pipecat/pipeline/pipeline.py | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index a02e700f2..754469167 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -38,6 +38,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Fixed an issue where `AsyncAITTSService` had very high latency in responding by adding `force=true` when sending the flush command. +### Performance + +- `Pipeline` performance improvements by using direct mode. + ### Other - Added `14w-function-calling-mistal.py` using `MistralLLMService`. diff --git a/src/pipecat/pipeline/base_pipeline.py b/src/pipecat/pipeline/base_pipeline.py index a3b1e0b3e..b27467b01 100644 --- a/src/pipecat/pipeline/base_pipeline.py +++ b/src/pipecat/pipeline/base_pipeline.py @@ -19,9 +19,9 @@ class BasePipeline(FrameProcessor): metrics collection from their contained processors. """ - def __init__(self): + def __init__(self, **kwargs): """Initialize the base pipeline.""" - super().__init__() + super().__init__(**kwargs) @abstractmethod def processors_with_metrics(self) -> List[FrameProcessor]: diff --git a/src/pipecat/pipeline/pipeline.py b/src/pipecat/pipeline/pipeline.py index 134639683..9a88c8426 100644 --- a/src/pipecat/pipeline/pipeline.py +++ b/src/pipecat/pipeline/pipeline.py @@ -98,7 +98,7 @@ class Pipeline(BasePipeline): Args: processors: List of frame processors to connect in sequence. """ - super().__init__() + super().__init__(enable_direct_mode=True) # Add a source and a sink queue so we can forward frames upstream and # downstream outside of the pipeline.